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| SL4017B Counter/Divider High-Voltage Silicon-Gate CMOS The SL4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles in the SL4017B. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C ORDERING INFORMATION SL4017BN Plastic SL4017BD SOIC T A = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply PIN 16 =VCC PIN 8 = GND SL S System Logic Semiconductor SL4017B FUNCTION TABLE Clock L X X Clock Enable X H X Reset Output State * L L H no change no change reset counter Q0=H, Q1Q9=L, C0=H Advance to next state no change no change Advance to next state L X X H L L L L * Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H Carry Out = L otherwise, X=don't care SL S System Logic Semiconductor SL4017B MAXIMUM RATINGS * Symbol VCC VIN VOUT I IN PD PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Unit V V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C * RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SL S System Logic Semiconductor SL4017B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Maximum LowLevel Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Minimum Output High (Source) Current Test Conditions VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.9 5 0.05 0.05 0.05 1.0 150 300 600 3000 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V VIL V VOH V VOL VIN=GND or VCC V I IN I CC VIN= GND or VCC VIN= GND or VCC A A I OL VIN= GND or VCC UOL =0.4 V UOL =0.5 V UOL =1.5 V VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V mA I OH SL S System Logic Semiconductor SL4017B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input tr =tf=20 ns) VCC Symbol fmax Parameter Maximum Clock Frequency V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55C 2.5 5 5.5 650 270 170 600 250 160 200 100 80 530 230 170 25C 2.5 5 5.5 650 270 170 600 250 160 200 100 80 530 230 170 5 125 C 1.25 2.5 2.75 1300 540 340 1200 500 320 400 200 160 1060 460 340 Unit MHz tPLH, tPHL Maximum Propagation Delay, Clock to Decode Output (Figure 1) Maximum Propagation Delay, Clock to Carry Output (Figure 1) Maximum Output Transition Time, Carry Output or Decode Output (Figure 1) Maximum Propagation Delay, Reset to Carry Output or Decode Output (Figure 1) Maximum Input Capacitance ns tPLH, tPHL ns tTLH, tTHL ns tPLH, tPHL ns CIN pF TIMING REQUIREMENTS (VCC=5.0V10%, C L=50pF, Input tr =tf=20 ns, RL=200k ) VCC Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 260 110 60 400 280 150 Guaranteed Limit -55C 200 90 60 25C 200 90 60 UNLIMITED 125 C 400 180 120 Unit ns tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 1) Minimum Removal Time, Reset (Figure 1) s tw 260 110 60 400 280 150 520 220 120 800 560 300 ns trem ns SL S System Logic Semiconductor SL4017B tSU Minimum Setup Time, Clock Inhibit to Clock (Figure 1) 5.0 10 15 230 100 70 230 100 70 460 200 140 ns SL S System Logic Semiconductor SL4017B Figure 1. Switching Waveforms Timing diagram SL S System Logic Semiconductor SL4017B EXPANDED LOGIC DIAGRAM SL S System Logic Semiconductor |
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